Multi-level low swing voltage values for low power design applications

A new low-power design method based on multiple low swing internal voltage values is proposed in this paper. It can be applied in logic circuits, which are designed with different logic family techniques such as Complementary Pass Transistor Logic (CPL), Domino Logic and Cascade Voltage Switch Logic (CVSL). The goal of this method is the reduction of the circuit power dissipation, with only a negligible increase in the area, without a reduction in the circuit operating speed. This is achieved with the replacement of a number of selected full swing voltage circuit components by low swing voltage components. The application of the proposed technique in a CPL 4-bit multiplier proved that 70% power dissipation reduction was achieved, with 30% area overhead, and no reduction in the circuit speed.